Data transmission among integrated circuit (IC) devices is performed through data signals that are driven by parallel channels of a data bus, the data signals being so-called data bits. The data bits may be sensitive to cross talk, simultaneous switching noise (SSN), inter-symbol interference (ISI), and/or power consumption, based on states of data or frequencies of data transition. In order to reduce these adverse effects, a data encoding method, such as data bus inversion (DBI), may be used. According to DBI, first, relationships between the data bits transmitted through the data bus are assessed, and then, before transmission of the data bits, it is determined whether it is effective to invert part or all of the data bits. When the data bits are inverted, an additional signal, that is, a DBI bit, which indicates that the data bits are inverted, may be set.
In order to support various systems, such as graphics, servers, super computers, networks, etc., for which high performance and low power consumption are required, high-bandwidth memory (HBM) can be provided, which is configured to provide wide input and output operations based on a multi-channel interface. The HBM may perform DBI in units of bytes in a channel including a plurality of data bits. Generally, DBI is performed when the number of data bits that are transitioned during data transmission is greater than half of all the data bits. When the DBI is applied, power consumption reduction, signal integrity (SI) improvement, heating reduction, etc., may be expected. In order to increase/maximize these effects, new DBI capable of reducing/minimizing the number of data transitions with respect to multiple-bit wide data, such as in HBM, may be desirable.